Fast multipliers for two´s-complement numbers in serial form

Schemes for designing multipliers of binary-two´s-complement numbers in serial form are considered with the condition of the least possible delay between inputs and output. Such schemes are composed by two parts: the first, the array generator, produces the terms of the multiplier array; the second, the summer, is fed by the array generator and produces the product. Two classes of multipliers are illustrated: the first generating the multiplier array by diagonals and rows, the second by columns. The array generators are composed by shift and/or stack registers and linear arrays of logic gates; the summer is shown to be conveniently built using parallel counters.