DocumentCode :
3401389
Title :
Squarers for binary numbers in serial form
Author :
Dadda, Luigi
Author_Institution :
Department of Electronics - Politecnico di Milano P.zza L. da Vinci 32, I-20133 Milano - Italy
fYear :
1985
fDate :
4-6 June 1985
Firstpage :
173
Lastpage :
179
Abstract :
The problem of designing squarers for binary number in serial form (with the condition of the least possible delay between input and output) is treated. Several schemes are Illustrated, derived from fast multipliers for binary numbers in serial form, described in a previous paper. It is shown that some of such multipliers offer a considerable saving in components when they are reduced to squarers. Some schemes are illustrated, both for positive and for two´s-complement numbers.
Keywords :
Adders; Arrays; Clocks; Delay; Generators; Logic gates; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Arithmetic (ARITH), 1985 IEEE 7th Symposium on
Conference_Location :
Urbana, IL,
Type :
conf
DOI :
10.1109/ARITH.1985.6158942
Filename :
6158942
Link To Document :
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