Title :
A performance-power evaluation of FinFET flip-flops under process variations
Author :
Munson, P.M. ; Delgado-Frias, Jose G.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
Abstract :
In this paper we present a performance-power study of three flip-flops using FinFET technology. First we tested the original designs with Monte Carlo variations, and then biased the back gate of the FinFETs. We report the following flip-flop delays: setup, clock to Q, and hold times. Setup and clock to Q times (called register delay) are in the pipeline stage critical path. Our study shows that the Low Delay (LDFF) flip-flop has the shortest register delay of 5.7ps. The flip-flop with the lowest power consumption is LPFF with 17.4 μW. Our simulations were performed using the University of Florida UFDG: Double-Gate MOSFET Model through the interface of Spice3f5 and Ngspice (ngspice3.ufdg-3.7) and a 32nm technology.
Keywords :
CMOS logic circuits; MOSFET; Monte Carlo methods; SPICE; delays; flip-flops; FinFET flip-flops; Monte Carlo variations; Ngspice interface; Spice3f5 interface; back gate; double-gate MOSFET model; flip-flop delays; ngspice3.ufdg-3.7; performance-power evaluation; pipeline stage critical path; power 17.4 muW; register delay; size 32 nm; Delay; Flip-flops; Registers; USA Councils; FinFET; Flip-flop performance; Monte Carlo; double-gate MOSFET; low power registers; register delay;
Conference_Titel :
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-61284-856-3
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2011.6026271
