Title :
Analog VLSI neural network implementations of hardware annealing and winner-take-all functions
Author :
Choi, Joongho ; Sheu, Bing J. ; Gowda, Sudhir M.
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
Hardware annealing and winner-take-all (WTA) functions have been implemented in 2.0-μm technology. The hardware annealing technique has been demonstrated using a 4×4 synapse network. Measurement results of a new WTA circuit are presented. The WTA circuit uses transistors biased in saturation to achieve high-speed performance. Since the comparison among the inputs is performed on one common signal line, the circuit can be easily extended to a larger dimension with that common signal line connected throughout the entire circuit. The new high-speed analog winner-take-all circuit can be extended linearly to at least 1024 inputs
Keywords :
VLSI; analogue processing circuits; neural nets; 2.0 micron; WTA circuit; common signal line; hardware annealing; synapse network; winner-take-all functions; Circuit simulation; Hopfield neural networks; Neural network hardware; Neural networks; Neurons; Resistors; Signal processing; Simulated annealing; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 1991., Proceedings of the 34th Midwest Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-0620-1
DOI :
10.1109/MWSCAS.1991.252167
