DocumentCode :
3402047
Title :
High speed CMOS vision chips
Author :
Nanjian Wu
Author_Institution :
State Key Lab. for Super Lattices & Microstructures, Chinese Acad. of Sci., Beijing, China
fYear :
2011
fDate :
7-10 Aug. 2011
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents novel high speed vision chips based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel processors and an embedded microprocessor unit. The multiple-levels of SIMD parallel processors consist of an array processor of SIMD processing elements (PEs) and a column of SIMD row processors (RPs). The PE array and RPs have an O(N×N) parallelism and an O(N) parallelism, respectively. The PE array, RPs and MPU can execute low-, mid- and high-level image processing algorithms, respectively. Prototype chips are fabricated using the 0.18μm CMOS process. Applications including target tracking, pattern extraction and image recognition are demonstrated.
Keywords :
CMOS image sensors; image processing; image recognition; parallel processing; CMOS image sensor; O(N×N) parallelism; O(N) parallelism; SIMD parallel processors; SIMD processing element array processor; SIMD row processors; embedded microprocessor unit; high speed CMOS vision chips; high-level image processing algorithm; image recognition; low-level image processing algorithm; mid-level image processing algorithm; parallel processor multiple levels; pattern extraction; size 0.18 mum; Complexity theory; Image recognition; Morphology; Parallel processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
Conference_Location :
Seoul
ISSN :
1548-3746
Print_ISBN :
978-1-61284-856-3
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2011.6026285
Filename :
6026285
Link To Document :
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