DocumentCode :
3402520
Title :
A multi-functional dot product unit with SIMD architecture for embedded 3D graphics engine
Author :
Yisong Chang ; Jizeng Wei ; Wei Guo ; Jizhou Sun
Author_Institution :
Sch. of Comput. Sci. & Technol., Tianjin Univ., Tianjin, China
fYear :
2011
fDate :
7-10 Aug. 2011
Firstpage :
1
Lastpage :
4
Abstract :
The floating-point 4D vector dot product (DP4) unit is the key factor to the overall performance of embedded graphics engine. In this paper, an enhanced multi-functional DP4 unit with optimized single instruction multiple data (SIMD) architecture is proposed, in which basic vector multiplication, addition and comparison in 3D graphics applications can be combined with specific dot production. To reduce area overhead, several fundamental hardware modules in the proposed DP4 unit are multiplexed and vectorized for SIMD functions instead of additional discrete floating-point multipliers and adders. The proposed methods can also avoid significant critical path delay increase so that the high performance of entire shader applications can be maintained. Normalization and rounding logics for SIMD vector addition function running in parallel with fundamental blocks and not affecting the critical path are also implemented. The synthesized result shows that the proposed multi-functional DP4 unit provides high performance with no critical path delay increase while just costs only 17% increase in area. The design can also be fully pipelined with a latency of 4 cycles and 1 cycle throughput at 193 MHz clock speed.
Keywords :
adders; computer architecture; computer graphic equipment; embedded systems; floating point arithmetic; parallel processing; 3D graphics applications; SIMD architecture; SIMD functions; SIMD vector addition function; basic vector multiplication; critical path delay; discrete floating-point adders; discrete floating-point multipliers; embedded 3D graphics engine; frequency 193 MHz; hardware modules; multifunctional DP4 unit; multifunctional dot product unit; optimized single instruction multiple data architecture; shader applications; Lead;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
Conference_Location :
Seoul
ISSN :
1548-3746
Print_ISBN :
978-1-61284-856-3
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2011.6026308
Filename :
6026308
Link To Document :
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