Systematic design of three-stage op-amps using split-length compensation

Over the past decade CMOS technology has been continuously scaling which has resulted in sustained improvement in transistor speeds. However, the transistor threshold voltages do not decrease at the same rate as the supply voltage (V_DD). Besides, the open-loop gain available from the transistors is diminishing. This trend renders the traditional techniques, like cascoding and gain boosting, less useful for achieving high DC gain in nano-scale CMOS processes. Thus, horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low-V_DD processes. This paper presents a design procedure for op-amp design using split-length compensation. A reversed-nested split-length compensated (RSLC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RSLC topology is then extended to the design of three-stage fully-differential op-amps.