A 4mW 3-tap 10 Gb/s decision feedback equalizer

A half-rate low-power 3-tap decision feedback equalizer (DFE) was designed in 90-nm CMOS technology. An improved switched-capacitor-based summer architecture is used in the front-end sample-and-hold to speculate the first feedback tap. Other two taps are canceled using current summation technique. Further power consumption reduction is achieved by using sense-amplifier-based slicer and pass-gate multiplexer instead of CML architecture. An accurate characterization of DFE, based on Least Square Estimation and using random sequence, with certain probabilistic characteristics suitable for intended operating conditions, is described. The Proposed 3-tap DFE consumes 4 mW from a 1.2 V supply when equalizing 10 Gb/s data passed over a 10" NELCO channel with 15 dB of loss at 5 GHz.