DocumentCode
34028
Title
Delay Test for Diagnosis of Power Switches
Author
Khursheed, Saqib ; Kan Shi ; Al-Hashimi, B.M. ; Wilson, Peter R. ; Chakrabarty, Krishnendu
Author_Institution
Sch. of Electron. & Comput. Sci., Univ. of Southampton, Southampton, UK
Volume
22
Issue
2
fYear
2014
fDate
Feb. 2014
Firstpage
197
Lastpage
206
Abstract
Power switches are used as a part of the power-gating technique to reduce the leakage power of a design. To the best of our knowledge, this is the first report in open literature to show a systematic diagnosis method for accurately diagnosing power switches. The proposed diagnosis method utilizes the recently proposed design-for-test solution for efficient testing of power switches in the presence of process, voltage, and temperature variation. It divides power switches into segments such that any faulty power switch is detectable, thereby achieving high diagnosis accuracy. The proposed diagnosis method is validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that, when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; it is less than 12% when considering VT variations.
Keywords
fault diagnosis; switches; ISCAS benchmarks; SPICE simulation; VT variation; delay test; design-for-test solution; diagnosis accuracy; faulty power switch detection; gate library; leakage power reduction; power switch diagnosis; power switch testing; power-gating technique; process variation; size 90 nm; systematic diagnosis method; temperature variation; voltage variation; Accuracy; Circuit faults; Delay; Discharges (electric); Discrete Fourier transforms; Logic gates; Transistors; Design for test (DFT); diagnosis; leakage power management; power gating; sleep transistor;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2013.2239319
Filename
6423290
Link To Document