• DocumentCode
    3402938
  • Title

    Patil array-a Petri net hardware implementation

  • Author

    Hartenstein, R.W. ; Hirschbiel, A. ; Weber, M.

  • Author_Institution
    Dept. of Comput. Sci., Kaiserslautern Univ., West Germany
  • fYear
    1988
  • fDate
    11-14 Apr 1988
  • Firstpage
    26
  • Lastpage
    33
  • Abstract
    The authors describe a parallel hardware implementation of Petri nets using the Kolte array scheme. The main feature of the work is a way of solving accessing conflicts which can arise from parallelism within such arrays. A description is also given of an NMOS circuit technique, a Patil array generator, and a flexible field-reprogrammable Patil array circuit technique
  • Keywords
    cellular arrays; directed graphs; field effect integrated circuits; integrated logic circuits; logic design; Kolte array scheme; NMOS circuit technique; Patil array generator; Petri nets; flexible field-reprogrammable Patil array circuit technique; parallel hardware implementation; Data structures; Graphics; Hardware;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    CompEuro '88. 'Design: Concepts, Methods and Tools'
  • Conference_Location
    Brussels
  • Print_ISBN
    0-8186-0834-X
  • Type

    conf

  • DOI
    10.1109/CMPEUR.1988.4931
  • Filename
    4931
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3402938