Layout regularity metric as a fast indicator of high variability circuits

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Layout regularity is one of the trending techniques suggested by design for manufacturability (DFM) to mitigate process variations effect. However, there is no study relating either lithography or electrical variations to layout regularity. In this paper, a novel method is presented to model electrical variations due to systematic lithographic variations. Then, geometrical-based layout regularity metric was derived; this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The metric results compared to the electrical variability model results show matching percentage that can reach 80%. Calculation of the metric takes only few minutes on 1 mm × 1 mm.