DocumentCode :
3402987
Title :
Sign detection in the Symmetric Residue Number System
Author :
Kaushik, Saroj ; Arora, R.K.
Author_Institution :
Computer Centre, Indian Institute of Technology, Delhi New Delhi 110016, India
fYear :
1981
fDate :
16-19 May 1981
Firstpage :
146
Lastpage :
151
Abstract :
This paper is concerned with the algebraic sign detection of a number in the Symmetric Residue Number System, A new approach has been suggested which completely avoid the time consuming process of the Symmetric Mixed Radix Conversion (SMRC). An algorithm based on the above approach implementable in parallel for sign detection is also presented. The heriware representation of the above algorithm is shown. The time and hardware complexity required for the process have also bean computed.
Keywords :
Adders; Argon; Complexity theory; Computers; Hardware; Logic gates; Manganese;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Arithmetic (ARITH), 1981 IEEE 5th Symposium on
Conference_Location :
Ann Arbor, MI, USA
Type :
conf
DOI :
10.1109/ARITH.1981.6159278
Filename :
6159278
Link To Document :
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