Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation

This work proposes a novel Dual-Port (DP) 8T SRAM operation scheme. The scheme improves the Read stability and Write-ability, and allows asynchronous operation with arbitrary clock timing skew between two ports. It facilitates high performance, low-power and low V_MIN with minimum device and area overhead. Post-simulation results show almost no timing penalty for simultaneous same-row access and the performance is almost the same as that for one port operation.