Plenary speaker: “Processor-to-memory interface design methodologies for energy and performance efficiencies”

Fundamental design goals for an SOC system including one or several processors often include lowest energy to accomplish the purpose of the chip, performance that meets the needs of the application, and reasonable hardware and software design effort to accomplish this. Often these don´t track in the same direction. The effort to improve one of these may affect another dramatically. The talk will discuss the development process of different interface methodologies toward this end with particular reference to processor to memory interfaces and the movement of data from one processor to another. Examples of specific uses of Dataplane Processors with high bandwidth data movement in current systems will be discussed along with some novel methods of data movement between processors. In addition, other opportunities for reducing Energy and Time in the use of Dataplane Processors in low power systems will be considered.