DocumentCode :
3403370
Title :
Compatible hardware for division and square root
Author :
Taylor, George S.
Author_Institution :
Computer Science Division, University of California Berkeley, California 94720
fYear :
1981
fDate :
16-19 May 1981
Firstpage :
127
Lastpage :
134
Abstract :
Hardware for radix four division and radix two square root is shared in a processor designed to implement the proposed IEEE floating-point standard. The division hardware looks ahead to find the next quotient digit in parallel with the next partial remainder. An 8-bit ALU estimates the next remainder´s leading bits. The quotient digit look-up table is addressed with a truncation of the estimate rather than a truncation of the full partial remainder. The estimation ALU and the look-up table are asymmetric for positive and negative remainders. This asymmetry reduces the width of the ALU and the number of minterms in the logic equations for thy look-up table. The square root algorithm obtains the correctly rounded result in about two division times using small extensions to the division hardware.
Keywords :
Delay; Equations; Flip-flops; Hardware; Redundancy; Registers; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Arithmetic (ARITH), 1981 IEEE 5th Symposium on
Conference_Location :
Ann Arbor, MI, USA
Type :
conf
DOI :
10.1109/ARITH.1981.6159293
Filename :
6159293
Link To Document :
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