A novel CMOS digital clock and data decoder for implanted systems

A novel all-digital clock and data separator (DCDS) using a CMOS 1.2 μm process is described. The DCDS is intended for an implantable bladder controller and can be used as a standard block for any programmable implanted prosthesis. All components used are digital and therefore unlike analog or hybrid decoders, the presented DCDS is not sensitive to fluctuating process parameters and can operate with different values of power supply. The proposed architecture is very simple and has been designed for low power that is an important parameter for implantable devices. A digital delay line provides the timing reference for the decoder with a programmable resolution. The DCDS meets the jitter-tolerance requirements and satisfies the exigency demand of implanted devices