A low-cost DDEM ADC structure for the testing of high-performance DACs

The testing of high resolution and high speed DACs (Digital-to-Analog Converters) is extremely challenging because of the requirements on the accuracy, speed and cost. This paper presents a new hardware overhead reduction method using DDEM (Deterministic Dynamic Element Matching) techniques for the testing of DACs. In this work, the proposed method make that resistors in a resistor string have different lengths by a merging operation. Accuracy of the proposed method is proven by theoretical analysis. The experimental results show that the proposed method reduces the usage of resources over 17%.