Title :
Real-time efficient FPGA implementation of aes algorithm
Author :
El Maraghy, Mazen ; Hesham, Salma ; Abd El Ghany, Mohamed A.
Author_Institution :
Electron. & Commun. Dept., German Univ. in Cairo, Cairo, Egypt
Abstract :
An efficient optimized area and speed FPGA implementation for the Advanced Encryption Standard is proposed in this paper. The iterative looping method is adopted with multistage sub-pipelining architecture to achieve a 1.33 Gbps throughput for the AES-128 bit Encryption process. The proposed design operates at 425 MHz with 303 CLB slices on a Xilinx Virtex-5 XC5VLX50 FPGA Device. For real-time hardware evaluation, an end-user Java based application is developed. The software application is linked to the hardware design through the Xilinx MicroBlaze soft processor core.
Keywords :
Java; cryptography; field programmable gate arrays; iterative methods; AES algorithm; AES-encryption process; CLB slices; Xilinx MicroBlaze soft processor core; Xilinx Virtex-5 XC5VLX50 FPGA device; advanced encryption standard; bit rate 1.33 Gbit/s; end-user Java based application; frequency 425 MHz; iterative looping method; multistage sub-pipelining architecture; optimized area FPGA; real-time efficient FPGA; real-time hardware evaluation; software application; speed FPGA; word length 128 bit; Abstracts; Encryption; Hardware; Indexes; AES; FPGA; MicroBlaze; VHDL; cryptography; hardware implementation;
Conference_Titel :
SOC Conference (SOCC), 2013 IEEE 26th International
Conference_Location :
Erlangen
DOI :
10.1109/SOCC.2013.6749688
