Novel time-multiplexing bidirectional on-chip network

Efficient routing path configuration and congestion mitigation are key steps to improve the overall performance of an on-chip network. Traditional approaches to achieving these goals often involve with considerable hardware and power consumption overheads. In this work, a novel dynamically self-reconfigurable Time-Multiplexing (TM) control mechanism is proposed for the bidirectional Network-on-Chip (BiNoC) architecture to address this problem. In particular, using TM-BiNoC, efficient routing path configuration and congestion mitigation can be accomplished without demanding costly hardware overhead. Extensive simulation results showed that with TM-BiNoC, the performance of BiNoCs may be enhanced by more than 21% while consuming less than 6% hardware overhead.