Exploring the opportunity of optimizing sequencing elements in ASIC designs

An edge-triggered flip-flop is a de facto standard sequencing element in ASIC designs. As sequencing elements occupy increasing portion of timing and power, it is necessary to explore other types of elements. We identify pulsed-latch and dual edge-triggered flip-flop as two promising candidates. The challenges when they are employed for conventional ASIC design are identified, and potential solutions are addressed.