DocumentCode :
3403823
Title :
Tutorial: Macro-modeling for solving SOC physical design automation problems
Author :
Bazylevych, Roman ; Bazylevych, Lubov
Author_Institution :
Comput. Sci., Leningrad Electro-Tech. Inst., St. Petersburg, Russia
fYear :
2013
fDate :
4-6 Sept. 2013
Firstpage :
314
Lastpage :
314
Abstract :
Large-scale combinatorial optimization problems arise in many areas. One of them is SoC Design Automation. Such problems as partitioning, packaging, placement, routing and compaction are very complex. From mathematical point of view, these problems belong to intractable combinatorial. Optimization is especially important for VLSI, SOC and NoC design. The complication of the electronic circuit requires a further search for the new robust approaches to solve such problems with high quality. New basic approaches and algorithms were developed for the hierarchical circuit clustering, partitioning, packaging, and placement by hierarchically built clusters, as well as for flexible (topological-geometric) routing.
Keywords :
VLSI; circuit optimisation; integrated circuit design; integrated circuit modelling; logic partitioning; network routing; network-on-chip; system-on-chip; NoC design; SOC physical design automation problems; VLSI; flexible routing; hierarchical circuit clustering; hierarchically built cluster placement; large-scale combinatorial optimization problems; macromodeling; packaging; partitioning; topological-geometric routing; Books; Routing; System-on-chip; Tutorials;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOC Conference (SOCC), 2013 IEEE 26th International
Conference_Location :
Erlangen
ISSN :
2164-1676
Type :
conf
DOI :
10.1109/SOCC.2013.6749707
Filename :
6749707
Link To Document :
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