Stress free wafer bonded GaAs-on-Si photonic devices and circuits

The integration of photonic devices with silicon circuitry has been proposed as an enabling technology for the next generation optical transceivers, router interconnect fabrics, and local area network (LAN) switches. One prevalent hybrid integration technique, wafer fusion bonding, involves fusing two wafers with different lattice constants under high pressure and elevated temperature, such as 700°C for GaAs/Si in contaminant-free environments. In the case of GaAs and Si wafer fusion bonding, however, the large thermal mismatch between the two materials presents serious problems, such as GaAs epilayer cracking during sample cooling and GaAs substrate removal, the appearance of new dislocations and poor device reliability, etc. A low temperature bonding technique is therefore proposed to solve the stress problem in the fusion bonding of GaAs device material to a Si substrate