A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance

This paper presents a novel subthreshold 9T SRAM cell with row-based Word-Line (WL) and column-based data-aware Write Word-Lines (WWLs). The decoupled Read port and cross-point Write structure provide a disturb-free cell and facilitate bit-interleaving architecture to improve soft error immunity. Compared with a previous cross-point Write 9T subthreshold SRAM cell reported in the literature, the proposed 9T SRAM cell offers comparable stability with improved Read performance and variation-tolerance. Monte Carlo simulations based on UMC 40nm Low-Power (40LP) technology indicate that the BL access time improves by 15.35% to 17.37%, and the variation (τ of BL access time) improves by 5.12% to 9.22% for V_DD ranging from 0.3V to 0.6V. Based on a 72Kb SRAM macro design in UMC 40LP process, the proposed 9T cell achieves about 9% better chip access time (Ta) at SS corner for V_DD ranging from 0.3V to 0.45V.