A comprehensive operand-aware dynamic clock gating scheme for low-power Domino Logic

Domino Logic´s excessive power consumption limits its use to ICs with lax power budgets. A dynamic clock gating scheme for Domino that takes advantage of inactive portions of functional unit operands is proposed. Through efficient switching activity detection, activity-domain partitioning, and a specific multi-phase configuration, significant power saving is achieved in a 32-bit Kogge Stone Adder at the cost of increased setup time in the preceding pipeline stage.