Title :
FPGA based optimization for masked AES implementation
Author :
Zheng Yuan ; Yi Wang ; Jing Li ; Renfa Li ; Wei Zhao
Author_Institution :
Embedded Syst. & Networking Lab., Hunan Univ., Changsha, China
Abstract :
Masking methods are popularly used to defend against power analysis attacks in embedded systems. Apart from power analysis attack, there also exists glitch attack when porting the design to gate level. In this paper, we firstly divided the existing masking methods into different types according to their functions, masking value and applications. Secondly, we compared different masked S-box hardware implementation. Finally, we proposed the masked AES encryption with 32-bit and 128-bit data path hardware implementation. The experimental results show that our proposed design takes up less hardware resources and has the ability to defend against differential power analysis(DPA) and glitch attacks.
Keywords :
cryptography; embedded systems; field programmable gate arrays; optimisation; FPGA; advanced encryption standard; differential power analysis; embedded systems; gate level; glitch attack; hardware implementation; masked AES encryption; optimization; power analysis attacks; storage capacity 128 bit; storage capacity 32 bit; Application specific integrated circuits; Cryptography; Logic gates; Radio access networks; Read only memory; Wool;
Conference_Titel :
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-61284-856-3
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2011.6026388