Hardware friendly motion estimation algorithm and VLSI architecture for H.264/AVC coding

Author

Liu, Yingzhe ; Wang, Jinxiang ; Fu, FangFa

Author_Institution

Microelectron. Center, Harbin Inst. of Technol., Harbin, China

fYear

2011

fDate

12-16 Oct. 2011

Firstpage

320

Lastpage

323

Abstract

A simple and hardware-oriented motion estimation algorithm based on a 5×5 square shaped search pattern is presented in this paper. High performance VLSI architecture for this algorithm is proposed to increase the coding efficiency. Compared with full search algorithm, the algorithm can speed up 91% coding time with 0.15 dB Peak Signal to Noise Ratio (PSNR) loss and 4% bit rate increase on average. The frequency of the architecture is 200MHz with the 189k logic gates in SIMC 0.18 μm CMOS technology. This architecture has higher performance with less hardware cost than other several architectures and can be applied to high definition H.264/AVC coding in real time.

Keywords

CMOS integrated circuits; VLSI; data compression; logic gates; motion estimation; video coding; CMOS technology; H.264-AVC coding; PSNR; SIMC; frequency 200 MHz; gain 0.15 dB; hardware friend motion estimation algorithm; high performance VLSI architecture; logic gates; shaped search pattern; signal-to-noise ratio; size 0.18 mum; Algorithm design and analysis; Arrays; Encoding; Motion estimation; Random access memory; Very large scale integration; H.264/AVC; VLSI; motion estimation; video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Optoelectronics and Microelectronics Technology (AISOMT), 2011 Academic International Symposium on

Conference_Location

Harbin

Print_ISBN

978-1-4577-0794-0

Type

conf

DOI

10.1109/AISMOT.2011.6159382

Filename

6159382