Low power 12bit 50KS/s R-C SAR ADC implemented based on mismatch analysis

Author

Wang, Yongsheng ; Sun, Jingyao ; Yu, Mingyan ; Lai, Fengchang

Author_Institution

Micro-Electron. Dept., Harbin Inst. of Technol., Harbin, China

fYear

2011

fDate

12-16 Oct. 2011

Firstpage

340

Lastpage

343

Abstract

A low power 12bit 50KS/s R-C SAR (successive approximation) ADC is presented in this paper. A R-C DAC structure and modified sample-hold circuit are presented. For the digits distribution of R-C DAC, the mismatch analysis of capacitors and resistances is emphasized because precision of SAR ADC primarily depends on its DAC. Reasonable layout design can decrease the R-C DAC mismatch. A 12-bit resolution is achieved in 7-5 digits distribution structure of SAR ADC which operates with 1.8 V analog power and 1.8V digital power, is realized in 0.18 μm CMOS 1P6M technology. The SAR ADC draws only 0.54 mW of power and has a maximum conversion frequency of 50 KS/s and SFDR of 81 dB.

Keywords

CMOS integrated circuits; analogue-digital conversion; low-power electronics; sample and hold circuits; CMOS 1P6M technology; R-C DAC structure; layout design; low power R-C SAR ADC; mismatch analysis; power 0.54 mW; sample-hold circuit; size 0.18 mum; successive approximation; voltage 1.8 V; word length 12 bit; Arrays; Capacitors; Equations; Layout; Mathematical model; Power dissipation; Resistance; SAR ADC; capacitor matching; digital-to-analog converter; resistance matching;

fLanguage

English

Publisher

ieee

Conference_Titel

Optoelectronics and Microelectronics Technology (AISOMT), 2011 Academic International Symposium on

Conference_Location

Harbin

Print_ISBN

978-1-4577-0794-0

Type

conf

DOI

10.1109/AISMOT.2011.6159387

Filename

6159387