Title :
Low power design of a full adder standard cell
Author :
Jianping Hu ; Jun Wang
Author_Institution :
Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China
Abstract :
In this paper, a low-power full adder standard cell is introduced in SMIC 130nm CMOS libraries. The full adder standard cell is optimized to achieve low energy delay product (EDP). All circuits are simulated with HSPICE at a SMIC 130nm CMOS technology by a 1.2V supply voltage. The layout, abstract design and standard-cell characters of the low-power full adder are also described.
Keywords :
CMOS integrated circuits; SPICE; adders; logic design; low-power electronics; EDP; HSPICE; SMIC 130nm CMOS libraries; energy delay product; full adder standard cell; low power design; size 130 nm; voltage 1.2 V; Adders; CMOS integrated circuits; CMOS technology; Libraries; Pins; Timing;
Conference_Titel :
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-61284-856-3
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2011.6026457
