Title :
An improved method for RTL synthesis with testability tradeoffs
Author :
Harmanani, H. ; Papachristou, C.A.
Author_Institution :
Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
Abstract :
A method for high level synthesis with testability is presented with the objective to generate self-testable RTL datapath structures. We base our approach on a new improved testability model that generates various testable design styles while reducing the circuit sequential depth from controllable to observable registers. We follow the allocation method with an automatic test point selection algorithm and with an interactive tradeoff scheme which trades design area and delay with test quality. The method has been implemented and design comparisons are reported.
Keywords :
high level synthesis; RTL synthesis; allocation method; automatic test point selection algorithm; circuit sequential depth; design area; high level synthesis; interactive tradeoff scheme; register transfer level; self-testable RTL datapath structures; test quality; testability model; testability tradeoffs; testable design styles; Algorithm design and analysis; Automatic generation control; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; Delay; High level synthesis; Registers; Sequential analysis;
Conference_Titel :
Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-4490-7
DOI :
10.1109/ICCAD.1993.580027
