DocumentCode :
3405785
Title :
Bounds on net lengths for high-speed PCBs
Author :
Lee, J. ; Shragowitz, E. ; Poli, D.
Author_Institution :
Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
fYear :
1993
fDate :
7-11 Nov. 1993
Firstpage :
73
Lastpage :
76
Abstract :
In this paper, a methodology for computation of PCB and MCM net length bounds consistent with timing and noise constraints has been introduced. The length of lines and their segments is derived first from equations based on semiempirical formulas and these values of length are used as initial values for AWE-based simulation. For the simulated length of line, the delay at receivers is presented by multivariable Taylor series with respect to length of segments for multi-pin nets. Partial derivatives for this representation are computed numerically on AWE simulation step. Resulting linear delay functions are used in linear programming formulation to find maximal lengths consistent with timing bounds. This work will help to reduce a number of iterations in PCB and MCM design and thus influence a length of design cycle and quality of solutions.
Keywords :
circuit analysis computing; AWE-based simulation; MCM; PCB; computation; design cycle; linear delay functions; linear programming formulation; multi-pin nets; multivariable Taylor series; net length bounds; noise constraints; partial derivatives; printed circuit boards; semiempirical formulas; timing; timing bounds; Circuit noise; Computational modeling; Computer science; Crosstalk; Delay lines; Equations; Integrated circuit interconnections; Shape; Timing; Transmission lines;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-4490-7
Type :
conf
DOI :
10.1109/ICCAD.1993.580033
Filename :
580033
Link To Document :
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