Bounds on net lengths for high-speed PCBs

In this paper, a methodology for computation of PCB and MCM net length bounds consistent with timing and noise constraints has been introduced. The length of lines and their segments is derived first from equations based on semiempirical formulas and these values of length are used as initial values for AWE-based simulation. For the simulated length of line, the delay at receivers is presented by multivariable Taylor series with respect to length of segments for multi-pin nets. Partial derivatives for this representation are computed numerically on AWE simulation step. Resulting linear delay functions are used in linear programming formulation to find maximal lengths consistent with timing bounds. This work will help to reduce a number of iterations in PCB and MCM design and thus influence a length of design cycle and quality of solutions.