DocumentCode
3406039
Title
A combined hierarchical placement algorithm
Author
Shin, H. ; Kim, C. ; Kim, W. ; Oh, M. ; Rhee, K. ; Choi, S. ; Chung, H.
Author_Institution
Dept. of Electron. Eng., Hanyang Univ., South Korea
fYear
1993
fDate
7-11 Nov. 1993
Firstpage
164
Lastpage
169
Abstract
A hierarchical placement algorithm which combines mincut partitioning and simulated annealing has been developed. The objective of mincut partitioning is to minimize the number of crossing nets while the objective of placement by simulated annealing is usually to minimize the total estimated wire-length. The combined placement algorithm can optimize both the routing density and the estimated wire-length. For efficiency, the placement is performed using multiple levels of hierarchy in the top-down direction, i.e., big groups of cells are placed at the beginning and leafcells are placed at the final level. Several standard-cell and sea-of-gates circuits are placed using the combined placement techniques and promising results are obtained when compared with those of several other placement methods.
Keywords
circuit layout; combined hierarchical placement algorithm; crossing nets; estimated wire-length; mincut partitioning; routing density; sea-of-gates circuits; simulated annealing; standard-cell; top-down direction; Central Processing Unit; Circuit simulation; Clustering algorithms; Costs; Delay; Partitioning algorithms; Routing; Simulated annealing; Temperature; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-4490-7
Type
conf
DOI
10.1109/ICCAD.1993.580050
Filename
580050
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