Architecture and routability analysis for row-based FPGAs

FPGAs combine the logic integration benefits of custom VLSI with the design, production, and time-to-market advantages of standard logic ICs. One class of FPGAs has rows of logic cells interspersed with routing channels have given this family of FPGA devices the flavor of traditional channeled gate arrays or standard cells. This class has the flavor of traditional channeled gate arrays or standard cells and is exemplified by the Actel family of FPGAs. However, unlike conventional standard cell designs, the FPGA routing channels contain predefined wiring segments of various lengths which may be interconnected using antifuses. This paper develops analytical models that permit the design of FPGA routing channels and the analysis of the routability of row-based FPGAs devices based on a generic characterization of the row-based FPGA routing algorithms. In particular, it demonstrates that (using probabilistic models for the origination point and length for connections) an FPGA with properly designed segment length and distribution can be nearly as efficient as a mask-programmable channel (in terms of number of tracks required for routing a given interconnection specification). Experimental results corroborate this prediction. In addition, this paper provides a method for evaluating various channel architectures.