• DocumentCode
    3406260
  • Title

    Partitioning with cone structures

  • Author

    Saucier, G. ; Brasen, D. ; Hiol, J.P.

  • Author_Institution
    Inst. Nat. Polytech. de Grenoble/CSI, France
  • fYear
    1993
  • fDate
    7-11 Nov. 1993
  • Firstpage
    236
  • Lastpage
    239
  • Abstract
    Circuit partitioning for packages that have limited numbers of IO pins is a critical problem with FPGAs. Common FPGAs have prespecified maximum gate count limits on the order of five to ten times the number of usable IO pins. Traditional min-cut approaches lack the ability to find such constrained partitions with high gate to IO pin ratios. In this paper, a new partitioning algorithm is presented that uses cone structures. Cone structures are minimum cut partitioning structures for netlists with low fanout, and clustering structures for partitioning netlists with high fanout. Cone structures also allow for full containment of critical paths. When used with good Merging/Cutting strategies, results show that the cone partitioning algorithms introduced here produce better partitions than min-cut.
  • Keywords
    programmable logic arrays; FPGAs; circuit partitioning algorithm; clustering structures; field programmable gate arrays; maximum gate count limits; min-cut approaches; minimum cut partitioning structures; netlists; Circuits; Clustering algorithms; Costs; Field programmable gate arrays; Iterative algorithms; Merging; Packaging; Partitioning algorithms; Pins; Production;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on
  • Conference_Location
    Santa Clara, CA, USA
  • Print_ISBN
    0-8186-4490-7
  • Type

    conf

  • DOI
    10.1109/ICCAD.1993.580063
  • Filename
    580063