A timing driven N-way chip and multi-chip partitioner

With the growing complexity of integrated circuits and the advent of new technologies and new generations of packaging technologies, an essential physical design tool is a flexible physical partitioner. We therefore present a timing driven n-way chip and multi-chip partitioner which we call Tomus. The partitioner enables an automatic layout package to (1) divide and conquer the physical design process of field programmable gate array (FPGA) circuits or mixed macro/standard cell circuits and (2) physically partition a circuit onto n chips for a multichip package. Using a two-phased natural and adaptive clustering method, the annealing-based N-way partitioner executes four to 22 times faster with improved partitioning results. The placement results for industrial FPGAs were improved by 90% over the only available industrial placement tool. Our partitioner outperformed an industrial FPGA partitioner by 95% in MCM partitioning.