Retiming gated-clocks and precharged circuit structures

This paper presents methods for retiming VLSI systems that contain precharged circuit structures and/or "gated" clock signals. Due to the tangible speed, power, and area benefits of circuit structures that utilize precharging techniques and/or gated clock signals, both are common in "high-performance" VLSI designs. Previous methods for performing retiming (i.e., optimizing the placement of latches) have not, however, addressed the pecularities of such circuit structures, and consequently, have not been applicable to many non-ASIC VLSI systems. The presented methods immediately lead to an algorithm which runs, to within a constant factor, in the same amount of time as previous retiming algorithms, yet is capable of handling precharged structures and gated clock signals. Using the algorithm, it is possible to apply retiming techniques to "full custom" VLSI designs. Though the paper focuses on the problem of retiming, the methods described are also applicable to the problem of timing verification. All results are based upon a general set of "timing" constraints which is directly applicable to circuits that contain precharged structures and gated clocks.