DocumentCode :
340660
Title :
Front-end readout system for PHENIX RICH
Author :
Tanaka, Y. ; Hara, H. ; Ebisu, K. ; Hibino, M. ; Matsumoto, T. ; Kikuchi, J. ; Wintenberg, A.L. ; Walker, J.W. ; Frank, S. ; Moscone, C. ; Jones, J.P. ; Young, G.R. ; Oyama, K. ; Hamagaki, H.
Author_Institution :
Inst. of Appl. Sci., Nagasaki Univ., Japan
Volume :
1
fYear :
1998
fDate :
1998
Firstpage :
346
Abstract :
A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, source synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with 128-bits data bus. The total transaction time is estimated to be less than 30 μs per event when this system is applied to the experiment. This result indicates that the performance is satisfied with the requirements of the PHENIX experiment
Keywords :
Cherenkov counters; high energy physics instrumentation computing; nuclear electronics; programmable logic devices; 640 byte/s; PHENIX; RICH; complex programmable logic devices; control bus; custom backplane; custom circuit modules; data bus; front-end readout system; source synchronous bus architecture; transfer speed; Analog memory; Backplanes; Circuit testing; Communication system control; Electron accelerators; Electron tubes; Laboratories; Photomultipliers; Programmable logic devices; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Nuclear Science Symposium, 1998. Conference Record. 1998 IEEE
Conference_Location :
Toronto, Ont.
ISSN :
1082-3654
Print_ISBN :
0-7803-5021-9
Type :
conf
DOI :
10.1109/NSSMIC.1998.775159
Filename :
775159
Link To Document :
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