DocumentCode :
3406624
Title :
New faster Kernighan-Lin-type graph-partitioning algorithms
Author :
Dutt, S.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear :
1993
fDate :
7-11 Nov. 1993
Firstpage :
370
Lastpage :
377
Abstract :
In this paper we present a very efficient graph partitioning scheme QuickCut that uses the basic strategy of the Kernighan-Lin (K-L) algorithm to swap pairs of nodes to improve an existing partition of a graph G. The main feature of QuickCut is a "neighborhood search" strategy that is based on the result (obtained in this paper) that it is not necessary to search more than a certain subset of d/sup 2/ node pairs to find the node pair with the maximum swap gain. Here d is the maximum node degree of G. We also use an improved data structure, viz., balanced trees, to store the nodes in the two partitions. Due to the new search strategy and data structure, QuickCut has a worst-case time complexity of /spl Theta/(max(ed, e log n)), and an average-case complexity of /spl Theta/(e log n), where e is the number of edges of G. The K-L algorithm, on the other hand, has a time complexity of /spl Theta/(n/sup 2/ log n), where n is the number of nodes of G. Another contribution of this paper is the presentation of efficient node-pair scanning methods for obtaining the best node pair to swap in the K-L algorithm. We have implemented QuickCut, K-L, and its various enhancements suggested here. The results obtained from using these different algorithms to partition a number of random and other well-defined graphs show that QuickCut is the fastest, and that it is faster than the K-L algorithm by factors of 5 to 50. Thus QuickCut can serve as the basis for very fast VLSI partitioning and layout tools.
Keywords :
circuit layout; Kernighan-Lin-type graph-partitioning algorithms; VLSI partitioning; graph partitioning scheme QuickCut; layout tools; maximum node degree; neighborhood search; node-pair scanning methods; Circuits; Costs; Genetic algorithms; Partitioning algorithms; Simulated annealing; Subspace constraints; Tree data structures; Very large scale integration; Wires; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-4490-7
Type :
conf
DOI :
10.1109/ICCAD.1993.580083
Filename :
580083
Link To Document :
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