State look ahead technique for cycle optimization of interacting finite state Moore machines

In the area of hardware design, automata is often realized synchronously by a clocked state register, a next state logic block representing the state transition function, and an output logic block representing the output function. Assuming that combinatorial blocks of automata are already optimized, a further potential for timing optimization occurs, if two Moore automata interact sequentially, where the output of the first automata is the input of the second one. Processing of an event that occurs as input of the first automaton by both automata needs up to two clock cycles: at most one clock for producing an output of the first one, and one clock cycle to compute the final output by the second one. In this paper an algorithm is presented that allows to avoid one clock cycle in certain well defined situations.