DocumentCode
3407172
Title
An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers
Author
Venkataraman, S. ; Rajski, J. ; Hellebrand, S. ; Tarnick, S.
Author_Institution
MACS Laboratory, McGill University, Montreal, Canada - H3A 2A7
fYear
1993
fDate
7-11 Nov. 1993
Firstpage
572
Lastpage
577
Abstract
In this paper we describe an optimized BIST scheme based on reseeding of multiple polynomial Linear Feedback Shift Registers (LFSRs). The same LFSR that is used to generate pseudo-random patterns, is loaded with seeds from which it produces vectors that cover the testcubes of difficult to test faults. The scheme is compatible with scandesign and achieves full coverage as it is based on random patterns combined with a deterministic test set.
Keywords
Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Encoding; Hardware; Linear feedback shift registers; Memory; Polynomials; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-4490-7
Type
conf
DOI
10.1109/ICCAD.1993.580117
Filename
580117
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