• DocumentCode
    3407300
  • Title

    An optimized hardware design for stereoscopic image generation based on depth image

  • Author

    Bing Liu ; Jizeng Wei ; Shaofei Shi ; Yisong Chang ; Wei Guo

  • Author_Institution
    Sch. of Comput. Sci. & Technol., Tianjin Univ., Tianjin, China
  • fYear
    2011
  • fDate
    7-10 Aug. 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Depth Image Based Rendering (DIBR) is the most popular method to generate stereoscopic images. In this paper, a novel pixel-level full-pipelined hardware accelerator is presented. The proposed architecture with division elimination algorithm and cache window design can achieve real-time rendering speed with low cost. The hardware design is implemented and verified on FPGA platform. The result shows the design can be applied to handheld devices due to its high efficiency.
  • Keywords
    cache storage; field programmable gate arrays; rendering (computer graphics); stereo image processing; FPGA; cache window design; depth image based rendering; division elimination algorithm; pixel-level full-pipelined hardware accelerator; stereoscopic image generation; Computer architecture;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
  • Conference_Location
    Seoul
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-61284-856-3
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2011.6026566
  • Filename
    6026566
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3407300