A Reuse Approach for FPGA-Based SDR Waveforms

Software targeting general purpose processing (GPP) elements has been successfully reused for software defined radio (SDR) platforms in support of low-bandwidth waveforms. The joint tactical radio system (JTRS) software communications architecture (SCA) promotes reuse of GPP-based software by providing a consistent framework for developing reusable waveform implementations. However, high-bandwidth waveforms, such as those used in above 2 GHz MILSATCOM terminals, overwhelm the capabilities of GPP-only radios making field programmable gate arrays (FPGAs) a necessity in high-bandwidth radio systems. The SCA does not address the development of reusable FPGA-based waveform implementations. This paper presents an approach supplementing the current SCA to address FPGA-based platforms using system-on-a-chip (SoC) best practices for design reuse, including common interfaces and a robust system simulation environment