Buffer assignment for data driven architectures

Data driven architectures have the potential to exhibit higher performance and throughput when compared to their control driven counterparts. In order to ensure that these performance gains are realized, it is required that the underlying data flow graph (DFG) have no accumulation of data at its nodes. Hence, all operands should arrive simultaneously at a multi-input operation node. Buffers are therefore inserted to ensure these conditions. An algorithm for buffer distribution in a balanced DFG of order (V /spl times/ E) is proposed. The number of buffers in the proposed buffer distribution strategy is equal to the minimum number of buffers achieved by integer programming techniques. An extension of this algorithm, of order (V/sup 2/ /spl times/ log V) is proposed which can further reduce the number of buffers by altering the DFG while keeping the functionality and performance of the DFG intact. Performance results showing the improvement of these algorithms over the existing ones have been shown.