A spacing algorithm for performance enhancement and cross-talk reduction

With the shrinking of feature size on silicon, the coupled capacitance between adjacent wires is contributing a significant factor to the interconnect delay, which already dominates the circuit performance. In the near future coupled capacitance could contribute as much as 50-75% to the interconnect delay which has been largely ignored by performance-oriented layout tools. Given a routed design, this work minimizes the delay and the peak cross-talk by re-adjusting the space between interconnects. It can reduce the circuit delay significantly and, in addition, reduce the peak cross-talk problem. An efficient technique based on the network simplex algorithm is used to solve the problem in the paradigm of compaction.