Efficient modeling of switch-level networks containing undetermined logic node states

The presence of realistic faults in CMOS networks, such as shorts and opens, frequently gives rise to intermediate voltage values. At the switch level, these values result in undetermined logic states which are likely to propagate to the outputs, causing an overly optimistic coverage estimation of test efficiency. A new method is presented that is efficient and well-suited for modeling switch-level networks when undetermined states are common. The concept of state dominance, introduced in this paper, is an improvement upon the well-known principle of dominance. The state dominance defines a dynamic direction of signal flow between neighboring nodes of undetermined logic state. A signal transformation scheme is proposed which solves bidirectional conflicts that may occur between adjacent nodes of undermined logic state without any network recomputation. The new concept is easily applicable to switch-level algorithms in which there is a distributed approach.