Comparison of charge sharing reduction techniques in deep sub-micron CMOS processes

Author

Haghi, M. ; Draper, J.

Author_Institution

Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

fYear

2011

fDate

7-10 Aug. 2011

Firstpage

1

Lastpage

4

Abstract

In this paper, we investigate and compare the effectiveness of different charge sharing techniques for reduction of charge sharing and collection among adjacent nodes in 65-nm technology NFET transistors. We use Synopsys 2-D TCAD mixed-mode simulations to measure collected charge at a node adjacent to a device struck by a heavy-ion particle for cases of using Shallow Trench Isolation (STI), Deep Trench Isolation (DTI), guard-ring and guard-diode; different nodal separations; and with particles of differing linear energy transfer (LET) strengths. The results show the most reduction in collected charge (more than 98%) at the adjacent node for DTI. Also, there is almost zero increase in area while using DTI; however, some pulse broadening at the struck node is observed.

Keywords

CMOS integrated circuits; field effect transistors; isolation technology; technology CAD (electronics); DTI; LET strength; NFET transistor; STI; Synopsys 2-D TCAD mixed-mode simulation; charge sharing reduction technique; deep submicron CMOS process; deep trench isolation; different nodal separation; guard-diode; guard-ring; heavy-ion particle; linear energy transfer; pulse broadening; shallow trench isolation; size 65 nm; Diffusion tensor imaging;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Conference_Location

Seoul

ISSN

1548-3746

Print_ISBN

978-1-61284-856-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2011.6026598

Filename

6026598