DocumentCode :
3408345
Title :
Superior latch-up resistance of high dose, high energy implanted p + buried layers
Author :
Leong, K.C. ; Liu, P. C Liu W ; Morris, W. ; Rubin, L. ; Gan, C.H. ; Chan, L.
Author_Institution :
Nanyang Technol. Inst., Singapore
Volume :
1
fYear :
1999
fDate :
1999
Firstpage :
99
Abstract :
Implantation of high dose, high energy blanket boron buried layers into p-type silicon is becoming increasingly attractive for leading edge CMOS technology. Implanted p+ buried layers provide several device and circuit benefits, such as superior latch-up immunity as compared to thin epi, and secondary defect gettering of other point defects. We have demonstrated that a 1×1015 cm-2 1.7 MeV boron buried layer combined with a low dose connecting layer produces latch-up trigger currents in excess of 1000 μA/μm, while the n+/p+ spacing was only 0.4 μm. This is much higher than what has been reported on epi substrates. The leakage currents for the 250 nm devices were significantly lower than the unimplanted controls or wafers with lower buried layer doses, indicating sucessful damage gettering. Other device parameters such as threshold voltage, saturation current and punch through voltage were unaffected by the buried layer. The unique properties of the implanted p+ buried layer provide the CMOS process designer with many technical advantages, as will be discussed
Keywords :
CMOS integrated circuits; boron; buried layers; elemental semiconductors; getters; ion implantation; leakage currents; semiconductor doping; silicon; 1.7 MeV; Si:B; boron buried layer; damage gettering; high dose high energy implanted p+ buried layers; high energy blanket boron buried layers; implanted p+ buried layer; latch-up immunity; latch-up resistance; latch-up trigger currents; leading edge CMOS technology; leakage currents; low dose connecting layer; n+/p+ spacing; p-type silicon; punch through voltage; saturation current; threshold voltage; unimplanted controls; Boron; CMOS process; CMOS technology; Circuits; Gettering; Joining processes; Leakage current; Process design; Silicon; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Ion Implantation Technology Proceedings, 1998 International Conference on
Conference_Location :
Kyoto
Print_ISBN :
0-7803-4538-X
Type :
conf
DOI :
10.1109/IIT.1999.812061
Filename :
812061
Link To Document :
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