Orthogonal transpose-RAM cell array architecture with alternate bit-line to bit-line contact scheme

Author

Kim, Kyung-Saeng ; Rho, Kwangmyoung ; Lee, Kwyro

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea

fYear

2001

fDate

2001

Firstpage

9

Lastpage

11

Abstract

An orthogonal RAM cell array architecture suitable for efficient transposing is proposed, and layout and simulation results are presented. The cell is developed to adopt folded bit-line sensing scheme area-efficiently. The proposed alternate bit-line to bit-line contact scheme in the orthogonal RAM cell array architecture leads to asymmetric bit-line sensing scheme and (i, 2i) bit-line transposing scheme, and results in fast response time of the sense amplifier and low power dissipation for restoring

Keywords

CMOS memory circuits; cellular arrays; integrated circuit layout; integrated circuit metallisation; low-power electronics; random-access storage; CMOS sense amplifiers; RAM cell array layout; alternate bit-line to bit-line contact scheme; asymmetric bit-line sensing scheme; fast response time; folded bit-line sensing scheme; layout pattern; low power dissipation; orthogonal RAM cell array architecture; orthogonal transpose RAM; transposing scheme; Capacitance; Computational modeling; Computer architecture; Computer science; Computer simulation; Contacts; Delay; Electronic mail; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, IEEE International Workshop on, 2001.

Conference_Location

San Jose, CA

Print_ISBN

0-7695-1242-9

Type

conf

DOI

10.1109/MTDT.2001.945222

Filename

945222