Title :
An approach for evaluation of redundancy analysis algorithms
Author :
Shoukourian, S. ; Vardanian, V. ; Zorian, Y.
Author_Institution :
Virage Logic Int, Yerevan, Armenia
Abstract :
An approach for design and evaluation of redundancy analysis algorithms based on vectors of preferences is proposed for memory devices with spare elements. Experiments on the application of the new algorithms for self-test and repair (STAR) type SRAM memories have shown the efficiency of the proposed approach
Keywords :
SRAM chips; built-in self test; integrated circuit testing; redundancy; SRAM; STAR; efficiency; memory devices; redundancy analysis algorithms; self-test and repair type memories; spare elements; vectors of preferences; Algorithm design and analysis; Automatic testing; Built-in self-test; Design methodology; Hardware; Logic design; Logic devices; Random access memory; Redundancy; System testing;
Conference_Titel :
Memory Technology, Design and Testing, IEEE International Workshop on, 2001.
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-1242-9
DOI :
10.1109/MTDT.2001.945228
