Title :
Transient faults in DRAMs: concept, analysis and impact on tests
Author :
AL-Ars, Zaid ; Van de Goor, Ad J.
Author_Institution :
Sect. Comput. Eng., Delft Univ. of Technol., Netherlands
Abstract :
Memory fault models have always been considered not to change with time. Therefore, tests constructed to detect sensitized faults need not take into consideration the time period between sensitizing and detecting the fault. In this paper; a new class of memory fault models is presented, where the time between sensitizing and detection should be considered. The paper also presents fault analysis results, based on defect injection and simulation, where transient faults have been observed. The impact of transient faults on testing is discussed and new detection conditions, in combination with a test, are given
Keywords :
DRAM chips; fault simulation; integrated circuit testing; integrated memory circuits; leakage currents; transient analysis; DRAMs; defect injection; defect simulation; detection conditions; fault analysis; functional fault models; leakage current mechanisms; memory fault models; memory testing; transient faults; Capacitors; Information technology; Random access memory; Testing; Thin film transistors; Transient analysis;
Conference_Titel :
Memory Technology, Design and Testing, IEEE International Workshop on, 2001.
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-1242-9
DOI :
10.1109/MTDT.2001.945229