Low adaptation-delay LMS adaptive filter part-I: Introducing a novel multiplication cell

In this two-part paper, we present an efficient approach for the implementation of delayed least mean square (DLMS) adaptive filter. To have satisfactory convergence performance of DLMS algorithm, we have reduced the adaptation delay and at the same time we have also reduced the critical path to support high input-sampling rate. For achieving lower adaptation-delay and to have area-delay-power efficient implementation, we have proposed a novel multiplication cell and we have optimized the number of pipeline latches across the time-consuming combinational blocks of the structure. From the synthesis results we find that the existing direct-form structure of [1] involves nearly 83% more area-delay product (ADP) and nearly 170% more energy-delay product (EDP) than the proposed one, in average, for filter orders N = 8, 16 and 32. The best of the existing systolic structures [2], similarly, involves nearly 21% more ADP and nearly 18% higher EDP than the proposed one for the same filter orders. In this part of the paper, we have reviewed the DLMS algorithm and introduced the proposed multiplication cell. Besides, we have discussed the proposed scheme to realize the proposed DLMS adaptive filter that supports high input sampling rate with satisfactory convergence performance. In the second part of this paper, we have presented the proposed structure for reducing the critical path with minimal number of pipeline stages and discussed relative performances of the proposed structure and existing structures.